High-sped integrated circuit Static Random Access Memory (SRAM) devices are widely used, for example as a cache memory of a system. Cache memory is increasingly being used as the difference in speeds between a Central Processing Unit (CPU) and a Dynamic Random Access Memory (DRAM) becomes greater. Standard SRAMs of 10-20 ns speed are typically being used in systems operating at speeds of 100 Mhz or less. Moreover, there is an increasing need for high-speed synchronous SRAMs of 100-220 Mhz speeds to accommodate increases in the clock frequencies of CPUs. Hence, synchronous SRAMs have been used as cache SRAMs in low-end personal computers as well as products such as high-end workstations and servers.
Synchronous SRAMs may be divided into synchronous pipeline types and synchronous burst types. The former may be used as a cache SRAM in Reduced Instruction Set Computer (RISC) chips, whereas the latter may be used as a cache SRAM for Complex Instruction Set Computer (CISC) chips such as those marketed by Intel and Motorola. The present invention relates to synchronous burst SRAM devices.
FIG. 1 is a schematic block diagram of a conventional synchronous burst SRAM, centered around a burst control scheme. For ease of explanation, a read/write control path is not shown.
Referring to FIG. 1, a conventional synchronous SRAM has an address buffering portion 1, a burst controlling portion 2, a clock generating portion 3, and a burst counting portion 4. In addition, a conventional synchronous SRAM further includes a memory cell array 5, a sense amplifying portion 6, an output data path/data storing portion 7, an output buffer 8, and an input/output pin 9. A conventional synchronous SRAM also includes an input buffering portion 10, an input data path/data storing portion 11, and a write driving portion 12.
In a conventional synchronous SRAM of FIG. 1, the transmission sequences of output data and input data are determined by controlling the sense amplifying portion 6 and the write driving portion 12, or a word line or column selection line of the memory cell array 5, using the burst address signal BSTAD. BSTAD is the output signal of the burst counting portion 4.
FIG. 2 is a timing diagram illustrating the burst read operation of a conventional synchronous SRAM shown in FIG. 1. Referring to FIG. 2, when a burst read operation is performed in the conventional synchronous SRAM of FIG. 1, the burst address (BSTAD) is generated in the burst counting portion 4, the data of a memory cell is sensed in the sense amplifying portion 6, and the sensed data is latched in the output data path/data storing portion 7, during each of cycles T2, T3, and T4 but not during the first and fifth cycles T1 and T5. Thus, the processes of sensing, latching, and outputting data are controlled by the burst counting portion 4 during every cycle of the system clock signal CLK.
When an ultra high-speed burst read operation is performed in a conventional synchronous SRAM, using a high-speed system clock signal CLK, the cycle time for generating burst addresses and sensing, latching, and outputting data may decrease, thus possibly causing errors in the synchronous SRAM. When the frequency of the system clock signal CLK increases and the periods of the cycles decrease, similar errors may occur during the burst write operation. Furthermore, it may be difficult to read or write data in pairs during a single cycle to implement a double data rate function in a conventional synchronous SRAM of FIG. 1.